The present disclosure relates generally to semiconductor devices, and more particularly to threshold voltage modifications in semiconductor devices.
P-type field effect transistors (pFET) formed on silicon containing substrates typically employ a gate structure including a boron (or other acceptor) doped p-type polysilicon layer as a gate electrode deposited on top of a silicon dioxide or silicon oxynitride gate oxide layer. The gate voltage is applied through this polysilicon layer to create an inversion channel in the n-type silicon underneath the gate oxide layer. For a pFET to work properly, the inversion should begin occurring at slightly negative voltages applied to the polysilicon (poly-Si) gate electrode. This occurs as a consequence of the band alignment for the gate stack structure. For example, a poly-Si/gate oxide/n-type silicon stack forms a capacitor that swings into inversion at around 0 V. The threshold voltage Vt, which can be interpreted as the voltage at which the inversion starts occurring, is therefore approximately 0 V. The exact value of the threshold voltages has some dependence on the doping level in the silicon substrate, and can be varied somewhat by choosing an appropriate substrate doping level. When p-type field effect transistors are fabricated using a dielectric, such as hafnium oxide or hafnium silicate, the flatband voltage of the device is shifted from its ideal position of close to about +1 V, to about 0+/−300 mV.